CDCVF25081PW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCVF25081PW
Manufacturer

TI
ChipWorker Part#

CW8639811
Category

Clock Chip, Timing IC
Package

TSSOP-16
Description

Zero Delay PLL Clock Driver Single 8MHz to 200MHz 16Pin TSSOP Tube
Documentation

Datasheet

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CDCVF25081PW Specifications

Attribute	Attribute Value

Part Number	CDCVF25081PW
Manufacturer	TI
ChipWorker Part#	CW8639811
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Frequency	200 MHz
Supply Voltage (DC)	3.30 V
Number of Outputs	8 Output
Supply Current	5.00 µA
Number of Circuits	1 Circuit
Number of Inputs	1 Input
Maximum Duty Cycle	57 %
Fall Time (Max)	3.3 ns
Fall Time (Max)	3.3 ns
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081 operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point loads.
Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN. All outputs operate at the same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a low state. Unlike many products containing PLLs, the CDCVF25081 does not require an external RC network. The loop filter for the PLL is included on-chip, minimizing component count, space, and cost.
Because it is based on a PLL circuitry, the CDCVF25081 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency signal at CLKIN and any following changes to the PLL reference.
The CDCVF25081 is characterized for operation from -40°C to 85°C.

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