DAC38J84IAAV - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

DAC38J84IAAV
Manufacturer

TI
ChipWorker Part#

CW5108800
Category

Digital to Analog, DAC IC
Package

FCBGA-144
Description

Quad-Channel, 16Bit, 2.5GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC) 144-FCBGA -40℃ to 85℃
Documentation

Datasheet

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DAC38J84IAAV Specifications

Attribute	Attribute Value

Part Number	DAC38J84IAAV
Manufacturer	TI
ChipWorker Part#	CW5108800
Category	Digital to Analog, DAC IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	144 Pin
Case/Package	FCBGA-144
Number of Outputs	4 Output
Number of Channels	4 Channel
Number of Bits	16 Bit
Power Dissipation	1859 mW
Sample Rate	2.50 Hz
Power Consumption	1.859 W
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1859 mW
Number of DACs	4 DAC
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	EAR99

Product Description

The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

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