DS90CR286MTD - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

DS90CR286MTD
Manufacturer

TI
ChipWorker Part#

CW40417900
Category

Interface IC, Interface Controller
Package

TSSOP-56
Description

LVDS Receiver 0.45V 56Pin TSSOP Tube
Documentation

Datasheet

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DS90CR286MTD Specifications

Attribute	Attribute Value

Part Number	DS90CR286MTD
Manufacturer	TI
ChipWorker Part#	CW40417900
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	56 Pin
Case/Package	TSSOP-56
Supply Voltage (DC)	3.30 V, 3.30 V (max)
Supply Current	105 mA
Power Dissipation	1630 W
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1610 mW
Supply Voltage	3V ~ 3.6V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Not Recommended for New Designs
Packaging	Tube
RoHS	Non-Compliant
Lead-Free Status	Contains Lead

Product Description

DESCRIPTION
The DS90CR285 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR286 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s).
The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables" smaller form factor.
FEATURES
• Single +3.3V Supply
• Chipset (Tx + Rx) Power Consumption <250 mW (typ)
• Power-Down Mode (<0.5 mW total)
• Up to 231 Megabytes/sec Bandwidth
• Up to 1.848 Gbps Data Throughput
• Narrow Bus Reduces Cable Size
• 290 mV Swing LVDS Devices for Low EMI
• +1V Common Mode Range (Around +1.2V)
• PLL Requires no External Components
• Both Devices are Offered in a Low Profile 56-Lead TSSOP Package
• Rising Edge Data Strobe
• Compatible with TIA/EIA-644 LVDS Standard
• ESD Rating > 7 kV
• Operating Temperature: −40°C to +85°C

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