DS90LV018ATM - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

DS90LV018ATM
Manufacturer

TI
ChipWorker Part#

CW21893503
Category

LVDS, M-LVDS, ECL, CML IC
Package

SOIC-8
Description

TEXAS INSTRUMENTS DS90LV018ATM LVDS Driver, LVDS Differential Line Receiver, 1.5ns, 9mA, -40℃, 85℃, 3V
Documentation

Datasheet

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DS90LV018ATM Specifications

Attribute	Attribute Value

Part Number	DS90LV018ATM
Manufacturer	TI
ChipWorker Part#	CW21893503
Category	LVDS, M-LVDS, ECL, CML IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	3.30 V, 3.30 V (max)
Supply Current	5.4 mA
Number of Channels	1 Channel
Number of Positions	8 Position
Power Dissipation	1025 W
Data Rate	400 Mbps
Power Consumption	18.0 W
Input Current (Min)	20 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1025 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
	expand all
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	Non-Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	5A991.b.1

Product Description

The DS90LV018ATM is a single CMOS differential Line Receiver designed for applications requiring ultra-low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400Mbps (200MHz) utilizing low voltage differential signaling (LVDS) technology. It accepts low voltage (350mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver also supports open, shorted and terminated (100R) input fail-safe. The receiver output will be high for all fail-safe conditions. The DS90LV018A has a flow-through design for easy PCB layout. The DS90LV018A and companion LVDS line driver provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.
Flow-through pin-out
Power down high impedance on LVDS inputs
Low power design (18mW at 3.3V static)
Interoperable with existing 5V LVDS networks
Accepts small swing (350mV) differential signal levels
Supports open, short and terminated input failsafe
50ps Differential skew (typical)

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