DS90LV110ATMT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

DS90LV110ATMT
Manufacturer

TI
ChipWorker Part#

CW77794000
Category

Clock Buffer, Driver, PLL IC
Package

TSSOP-28
Description

TEXAS INSTRUMENTS DS90LV110ATMT LVDS Driver, Data/Clock Distributor, LVDS, 145 ps, 160mA, -40℃, 85℃, 3V
Documentation

Datasheet

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DS90LV110ATMT Specifications

Attribute	Attribute Value

Part Number	DS90LV110ATMT
Manufacturer	TI
ChipWorker Part#	CW77794000
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	28 Pin
Case/Package	TSSOP-28
Supply Voltage (DC)	3.00V (min)
Number of Circuits	1 Circuit
Number of Positions	28 Position
Power Dissipation	2115 W
Data Rate	400 Mbps
Power Consumption	417 W
Input Current (Min)	10 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	2115 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	Non-Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The DS90LV110ATMT is a 1 to 10 Data/Clock Distributor utilizing LVDS (low voltage differential signalling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution/fan-out replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz. It accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATE by use of the enable pin.
Balanced output impedance
LVDS input failsafe
Receiver open, shorted and terminated input failsafe
Output channel-to-channel skew is 35ps (typical)
Differential output voltage (VOD) is 320mV (typical) with 100R termination load
LVDS receiver inputs accept LVPECL signals
Fast propagation delay (2.8ns typical)

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