EP1C6Q240C6N - Altera

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

EP1C6Q240C6N
Manufacturer

Altera
ChipWorker Part#

CW45625934
Category

FPGA Chip
Package

QFP-240
Description

FPGA Cyclone Family 5980 Cells 405.2MHz 130nm Technology 1.5V 240Pin PQFP
Documentation

Datasheet

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EP1C6Q240C6N Specifications

Attribute	Attribute Value

Part Number	EP1C6Q240C6N
Manufacturer	Altera
ChipWorker Part#	CW45625934
Category	FPGA Chip
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	240 Pin
Case/Package	QFP-240
Frequency	405.2 MHz
Supply Voltage (DC)	1.20 V
Number of Positions	240 Position
RAM Memory Size	92160 b
Number of I/O Pins	185 IO
Number of Inputs and Outputs	185 Input IO
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	1.425V ~ 1.575V
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Size-Height	3.4 mm
Operating Temperature	0℃ ~ 85℃ (TJ)
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99
HK STC License	NLR

Product Description

The EP1C6Q240C6N is a Cyclone® FPGA based on a 1.5V, 0.13µm features all-layer copper SRAM process with densities up to 5980 logic elements (LEs) and up to 92160-bits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640Mbps and 66- and 33MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. It contains a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.
Supports configuration through low-cost serial configuration device
Supports for LVTTL, LVCMOS, SSTL-2 and SSTL-3 I/O standards
High-speed (640Mbps) LVDS I/O support
Low-speed (311Mbps) LVDS I/O support
311Mbps RSDS I/O support
Up to two PLLs per device provide clock multiplication and phase shifting
Up to eight global clock lines with six clock resources available per logic array block (LAB) row
Supports for external memory, including DDR SDRAM, FCRAM and single data rate SDRAM
Supports for multiple intellectual property (IP) cores

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