EP2C20Q240C8N - Altera

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

EP2C20Q240C8N
Manufacturer

Altera
ChipWorker Part#

CW28255462
Category

FPGA Chip
Package

PQFP-240
Description

FPGA Cyclone II Family 18752 Cells 402.58MHz 90nm Technology 1.2V 240Pin PQFP
Documentation

Datasheet

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EP2C20Q240C8N Specifications

Attribute	Attribute Value

Part Number	EP2C20Q240C8N
Manufacturer	Altera
ChipWorker Part#	CW28255462
Category	FPGA Chip
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	240 Pin
Case/Package	PQFP-240
Frequency	402.58 MHz
Supply Voltage (DC)	1.20 V
RAM Memory Size	239616 b
Number of Gates	20000 Gate
Number of I/O Pins	315 IO
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	1.15V ~ 1.25V
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Size-Height	3.4 mm
Operating Temperature	0℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	3A991
HK STC License	NLR

Product Description

The EP2C20Q240C8N is a Cyclone® II FPGA with an extend density of 18752 logic elements (LEs) and provide up to 315 usable I/O pins and up to 1.1Mb of embedded memory. Cyclone II FPGA is manufactured on 300mm wafers using TSMC"s 90nm low-k dielectric process to ensure rapid availability and low cost. By minimizing silicon area, Cyclone II devices can support complex digital systems on a single chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who compromise power consumption and performance for low-cost, Altera"s latest generation of low-cost FPGAs-Cyclone II FPGA, offers 60 percent higher performance and half the power consumption of competing 90nm FPGA. It contains a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between logic array blocks (LABs), embedded memory blocks and embedded multipliers.
Embedded multipliers
Advanced I/O support
Flexible clock management circuitry
Altera megafunction and Altera MegaCore function support
Altera Megafunctions Partners Program (AMPPSM) megafunction support
Programmable bus-hold feature
Programmable output drive strength feature
Programmable delays from the pin to the IOE or logic array
Tri-state with weak pull-up on I/O pins before and during configuration
Programmable open-drain outputs
Series on-chip termination support

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