EP3C25F256C8N - Altera

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

EP3C25F256C8N
Manufacturer

Altera
ChipWorker Part#

CW20694500
Category

FPGA Chip
Package

FBGA-256
Description

FPGA Cyclone III Family 24624 Cells 402MHz 65nm Technology 1.2V 256Pin TFBGA
Documentation

Datasheet

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EP3C25F256C8N Specifications

Attribute	Attribute Value

Part Number	EP3C25F256C8N
Manufacturer	Altera
ChipWorker Part#	CW20694500
Category	FPGA Chip
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	256 Pin
Case/Package	FBGA-256
Frequency	320 MHz
Number of Positions	256 Position
RAM Memory Size	608256 b
Number of Inputs and Outputs	156 Input IO
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	1.15V ~ 1.25V
Supply Voltage (Max)	2.625 V
Supply Voltage (Min)	2.375 V
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Size-Length	17 mm
Size-Width	17 mm
Size-Height	1.8 mm
Operating Temperature	0℃ ~ 85℃ (TJ)
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	Yes
REACH SVHC Compliance Edition	2015/12/17
HK STC License	NLR

Product Description

The EP3C25F256C8N is a Cyclone® III FPGA consists of 24624 vertically arranged logic elements (LEs), 594kb of embedded memory and 66 18 x 18 embedded multipliers. The architecture includes highly efficient interconnect and low-skew clock networks, providing connectivity between logic structures for clock and data signals. The logic and routing core fabric is surrounded by I/O elements (IOEs) and phase-locked loops (PLLs). The low-power Cyclone® III FPGA family is the third generation in the Altera® Cyclone FPGA series. With its unprecedented combination of low power, high functionality, the Cyclone III FPGA family broadens the number of high-volume, cost-sensitive applications that can benefit from an FPGA. The Cyclone III LS variant extends the family with higher density, higher memory, smaller packages and security features to protect your intellectual property (IP).
4 Phase-locked loops
83 Differential channels
Hot-socketing operation support
Routing architecture optimized for design separation flow with the Quartus® II software
Ability to disable external JTAG port
Error detection (ED) cycle indicator to core
Internal oscillator enables system monitor and health check capabilities
High memory-to-logic and multiplier-to-logic ratio
High I/O count, low-and mid-range density devices for user I/O constrained applications
Remote system upgrade without the aid of an external controller
Dedicated cyclical redundancy code checker circuitry to detect single-event upset (SEU) issues

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