FAN7390MX - Fairchild

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

FAN7390MX
Manufacturer

Fairchild
ChipWorker Part#

CW45555314
Category

FET Driver
Package

SOIC-8
Description

Driver 600V 4.5A 2Out Hi/Lo Side Half Brdg Non-Inv 8Pin SOIC N T/R
Documentation

Datasheet

FAN7390MX Global Supplier

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FAN7390MX Specifications

Attribute	Attribute Value

Part Number	FAN7390MX
Manufacturer	Fairchild
ChipWorker Part#	CW45555314
Category	FET Driver
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	10.0V (min)
Rise/Fall Time	25ns, 20ns
Number of Outputs	2 Output
Output Current	4.5 A
Number of Positions	8 Position
Power Dissipation	625 mW
Rise Time	50 ns
Output Current (Max)	4.5 A
Fall Time	50 ns
Fall Time (Max)	50 ns
Fall Time (Max)	50 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	625 mW
Supply Voltage	10V ~ 22V
Supply Voltage (Max)	22 V
Supply Voltage (Min)	10 V
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Size-Length	5 mm
Size-Width	4 mm
Size-Height	1.5 mm
Operating Temperature	-40℃ ~ 150℃ (TJ)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The FAN7390MX is an input logic compatible monolithic High and Low Side Gate-Drive which can drive high speed MOSFETs and IGBTs that operate up to 600V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Its high-voltage process and common-mode noise cancelling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level shift circuit offers high-side gate driver operation up to VS=-9.8V typical for VBS=15V. The UVLO circuit prevents malfunction when VDD and VBS are lower than the specified threshold voltage.
Common-mode dv/dt noise cancelling circuit
Built-in under-voltage lockout for both channels
Matched propagation delay for both channels
Output in-phase with input

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