HCPL062N - Fairchild

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

HCPL062N
Manufacturer

Fairchild
ChipWorker Part#

CW8723604
Category

Optocoupler, Optoisolator
Package

SOIC-8
Description

FAIRCHILD SEMICONDUCTOR HCPL062N Optocoupler, Digital Output, 2Channel, 2.5kV, 10Mbps, SOIC, 8Pins
Documentation

Datasheet

HCPL062N Global Supplier

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HCPL062N Specifications

Attribute	Attribute Value

Part Number	HCPL062N
Manufacturer	Fairchild
ChipWorker Part#	CW8723604
Category	Optocoupler, Optoisolator
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Rise/Fall Time	16ns, 4ns
Output Voltage	7 V
Output Current	0.015 A
Number of Channels	2 Channel
Number of Positions	8 Position
Forward Voltage	1.75V (Max)
Input Current	15 mA
Power Dissipation	0.085 W
Data Rate	10.0 Mbps
Rise Time	16 ns
Isolation Voltage	2500 Vrms
Forward Current	50 mA
Input Current (Min)	50 mA
Reverse Breakdown Voltage	5 V
Maximum Forward Voltage (Max)	1.75 V
Forward Current (Max)	50 mA
Fall Time	4 ns
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	85 mW
Supply Voltage	2.7V ~ 3.3V
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Size-Height	3.43 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The HCPL062N is a 2-channel 8-pin Logic Gate Optocoupler consists of an AlGaAs, LED optically coupled to a very high speed integrated photodetector logic gate consisting of bipolar transistors on a CMOS process for reduced power consumption. The output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40 to +85°C. An internal noise shield and provides superior common mode rejection. It is suitable for ground loop elimination, field buses, line receiver, data multiplexing and pulse transformer replacement.
Logic gate output
Wired OR-open collector
Fixed threshold detector design minimizes thermal impact on switching times
25kV/µs Minimum superior CMR (1000V common mode)

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