HD64F7047FW40 - Renesas Electronics

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

HD64F7047FW40
Manufacturer

Renesas Electronics
ChipWorker Part#

CW616189867
Category

Active Chip
Description

SH-2 SuperH SH7047 Microcontroller IC 32Bit 40MHz 256KB (256K x 8) FLASH 100-QFP (14x14)
Documentation

Datasheet

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HD64F7047FW40 Specifications

Attribute	Attribute Value

Part Number	HD64F7047FW40
Manufacturer	Renesas Electronics
ChipWorker Part#	CW616189867
Category	Active Chip
Documentation	Datasheet
Mounting Style	Surface Mount
Case/Package	BFQFP-100
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Clock Speed	40.0 MHz, 40.0 MHz (max)
RAM Memory Size	12K x 8
Number of I/O Pins	53 IO
Access Time	40.0 µs
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Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Unknown
Packaging	Tray
RoHS	Non-Compliant
Lead-Free Status	Contains Lead

Product Description

Overview
The SH7047 group single-chip RISC (Reduced Instruction Set Computer) microprocessors integrate a Renesas-original RISC CPU core with peripheral functions required for system configuration.
The SH7047 group CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds.
In addition, the SH7047 group includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, timers, a serial communication interface (SCI), Controller area network 2 (HCAN2), an A/D converter, an interrupt controller (INTC), and I/O ports. ROM and SRAM can be directly connected to the SH7047 MCU by means of an external memory access support function. This greatly reduces system cost.
Features
• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture
- Instruction length: 16-bit fixed length for improved code efficiency
- Load-store architecture (basic operations are executed between registers)
- Sixteen 32-bit general registers
- Five-stage pipeline
- On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) executed in two to four cycles C language-oriented 62 basic instructions
• Various peripheral functions
- Data transfer controller (DTC)
- Multifunction timer/pulse unit (MTU)
- Motor management timer(MMT)
- Compare match timer (CMT)
- Watchdog timer (WDT)
- Asynchronous or clocked synchronous serial communication interface(SCI)
- 10-bit A/D converter
- Clock pulse generator
- Controller area network2 (HCAN2)
- User break controller (UBC)
- High-performance user debug interface (H-UDI)
- Advanced user debugger (AUD)

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