HEF4017BP - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

HEF4017BP
Manufacturer

NXP
ChipWorker Part#

CW99428306
Category

Counter, Counter IC
Package

DIP-16
Description

Logic IC - Counter NXP Semiconductors 4017 Counter, Tenth 4000B Positive, Negtive 30MHz DIP 16
Documentation

Datasheet

HEF4017BP Global Supplier

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HEF4017BP Specifications

Attribute	Attribute Value

Part Number	HEF4017BP
Manufacturer	NXP
ChipWorker Part#	CW99428306
Category	Counter, Counter IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Supply Voltage (DC)	4.50V (min)
Number of Positions	16 Position
Clock Speed	30 MHz
Number of Gates	1 Gate
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	15.5 V
Supply Voltage (Min)	4.5 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The HEF4017BP is a 5-stage Johnson Decade Counter with ten spike-free decoded active high outputs (Q0 to Q9), an active low carry output from the most significant flip-flop (Q5-9), active high and active low clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a low-to-high transition at CP0 while CP1 is LOW or a high-to-low transition at CP1 while CP0 is high. When cascading counters, the Q5-9 output, which is low while the counter is in states 5, 6, 7, 8 and 9 can be used to drive the CP0 input of the next counter. A high on MR resets the counter to zero (Q0=Q5-9=high; Q1 to Q9=low) independent of the clock inputs (CP0, CP1). Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.
Automatic counter correction
Tolerant of slow clock rise and fall times
Fully static operation
Standardized symmetrical output characteristics

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