HEF4017BT - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

HEF4017BT
Manufacturer

NXP
ChipWorker Part#

CW105207438
Category

Counter, Counter IC
Package

SOIC
Description

IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 10Bit UP RING COUNTER, PDSO16, 3.9MM, PLASTIC, SOT109-1, SO-16, Counter
Documentation

Datasheet

HEF4017BT Global Supplier

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HEF4017BT Specifications

Attribute	Attribute Value

Part Number	HEF4017BT
Manufacturer	NXP
ChipWorker Part#	CW105207438
Category	Counter, Counter IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC
Supply Voltage (DC)	15.0 V
Number of Positions	16 Position
Clock Speed	30 MHz
Number of Gates	1 Gate
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	15 V
Supply Voltage (Min)	3 V
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Product Lifecycle Status	Unknown
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The HEF4017BT is a 5-stage Johnson Decade Counter with ten spike-free decoded active high outputs (Q0 to Q9), an active low carry output from the most significant flip-flop (Q5\\-9), active high and active low clock inputs (CP0, CP1\\) and an overriding asynchronous master reset input (MR). The counter is advanced by either a low-to-high transition at CP0 while CP1\ is low or a high-to-low transition at CP1\ while CP0 is high. When cascading counters, the Q5\\-9 output, which is low while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A high on MR resets the counter to zero (Q0 = Q5\\-9 = high, Q1 to Q9 = low) independent of the clock inputs (CP0, CP1\\). Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times.
Automatic counter correction
Tolerant of slow clock rise and fall times
Fully static operation
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B

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