HEF4027BT - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

HEF4027BT
Manufacturer

NXP
ChipWorker Part#

CW99428229
Category

Flip Flop IC
Package

SOIC
Description

IC 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 3.9MM, PLASTIC, MS-012, SOT109-1, SOP-16, FF/Latch
Documentation

Datasheet

HEF4027BT Global Supplier

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HEF4027BT Specifications

Attribute	Attribute Value

Part Number	HEF4027BT
Manufacturer	NXP
ChipWorker Part#	CW99428229
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC
Frequency	30 MHz
Supply Voltage (DC)	4.50V (min)
Output Current	2.4 mA
Number of Positions	16 Position
Number of Gates	2 Gate
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	15.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	10 mm
Size-Width	4 mm
Size-Height	1.45 mm
Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The HEF4027BT is a dual JK Flip-flop features independent set-direct (SD), clear-direct (CD), clock inputs and outputs (Q, Q\\). Data is accepted when clock is low and transferred to the output on the positive-going edge of the clock. The active high asynchronous clear-direct and set-direct inputs are independent and override the J, K and clock inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.
Fully static operation
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B

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- Anti-static packaging
- Anti-vibration foam
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- Surface testing

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