HEF4040BT - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

HEF4040BT
Manufacturer

NXP
ChipWorker Part#

CW128206769
Category

Counter, Counter IC
Package

SOIC
Description

IC 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 12Bit UP BINARY COUNTER, PDSO16, 3.9MM, PLASTIC, SOT109-1, MS-012, SOP-16, Counter
Documentation

Datasheet

HEF4040BT Global Supplier

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HEF4040BT Specifications

Attribute	Attribute Value

Part Number	HEF4040BT
Manufacturer	NXP
ChipWorker Part#	CW128206769
Category	Counter, Counter IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC
Frequency	50 MHz
Supply Voltage (DC)	4.50V (min)
Number of Positions	16 Position
Clock Speed	50 MHz
Number of Gates	1 Gate
Number of Inputs	1 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	15 V
Supply Voltage (Max)	15.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	10 mm
Size-Width	4 mm
Size-Height	1.45 mm
Operating Temperature	-40℃ ~ 70℃
Product Lifecycle Status	Unknown
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The HEF4040BT is a 12-stage Binary Ripple Counter with a clock input (CP\\), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the high-to-low transition of CP\\. A high on MR clears all counter stages and forces all outputs low, independent of CP\\. Each counter stage is a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its Schmitt trigger action. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.
Tolerant of slow clock rise and fall time
Fully static operation
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B

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