HMC988LP3E - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

HMC988LP3E
Manufacturer

ADI
ChipWorker Part#

CW1464793
Category

Clock Generator IC
Package

QFN-16
Description

Clock Generator 4000MHz-OUT 16Pin QFN EP T/R
Documentation

Datasheet

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HMC988LP3E Specifications

Attribute	Attribute Value

Part Number	HMC988LP3E
Manufacturer	ADI
ChipWorker Part#	CW1464793
Category	Clock Generator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	QFN-16
Number of Outputs	1 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3.1V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	3.1 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Contains Lead
ECCN Code	EAR99

Product Description

Product Details
The HMC988LP3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32. It is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option. Housed in a compact 3x3 mm SMT QFN package, the clock divider offers a high level of functionality. The device works with 3.3V supply or may be connected to 5V supply and utilize the optional on-chip regulator. This on-chip regulator may be bypassed. Up to 8 addressable HMC988LP3E devices can be used together on the SPI bus. The HMC988LP3E is ideally suited for data converter applications with extremely low phase noise requirements.
Applications
Basestation Digital Pre-Distortion Paths (DPD)
High Performance Automated Test Equipment (ATE)
Backplane Clock Skew Management
Phase Coherence of Multiple Clock Paths
Clock Delay Management ton Improve Setup & Hold Time Margins
PCB Signal Flight Time Offset Circuits
Track and Hold Circuits for ADC/DACs
### Features and Benefits
Programmable Clock Divide by 1/2/4/8/16/32
Delay Adjustment in Multiples of 1/2 Clock Cycles or in 60 Steps of 20 ps (Typ.)
-170 dBc/Hz Noise Floor @ 100 MHz Output
Up to 4 GHz Operation with 800 mVp-p LVPECL Output
3.3V Operation (or 5V Operation with Optional On-Chip Regulator for Best Performance)

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