IR2010PBF - Infineon

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

IR2010PBF
Manufacturer

Infineon
ChipWorker Part#

CW9101559
Category

FET Driver
Package

PDIP-14
Description

MOSFET DRVR 200V 3A 2Out Hi/Lo Side Non-Inv 14Pin PDIP Tube
Documentation

Datasheet

IR2010PBF Global Supplier

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IR2010PBF Specifications

Attribute	Attribute Value

Part Number	IR2010PBF
Manufacturer	Infineon
ChipWorker Part#	CW9101559
Category	FET Driver
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	14 Pin
Case/Package	PDIP-14
Supply Voltage (DC)	10.0V (min)
Operating Voltage	10V ~ 20V
Rise/Fall Time	10ns, 15ns
Number of Outputs	2 Output
Output Voltage	220 V
Number of Positions	14 Position
Power Dissipation	1600 mW
Rise Time	20ns (Max)
Fall Time	25ns (Max)
Fall Time (Max)	25 ns
Fall Time (Max)	20 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1600 mW
Supply Voltage	10V ~ 20V
Supply Voltage (Max)	20 V
Supply Voltage (Min)	10 V
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Size-Length	20.19 mm
Size-Width	7.11 mm
Size-Height	4.94 mm
Operating Temperature	-40℃ ~ 150℃ (TJ)
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The IR2010PBF is a high power high voltage high speed power MOSFET and IGBT Driver with independent high and low-side referenced output channels. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3V logic. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 200V. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction.
Floating channel designed for bootstrap operation
Tolerant to negative transient voltage (dV/dt immune)
Under-voltage lockout for both channels
3.3V Logic compatible
Logic and power ground ±5V offset
CMOS Schmitt-triggered inputs with pull-down
Shut down input turns OFF both channels
Cross-conduction prevention logic
Matched propagation delay for both channels
Outputs in phase with inputs

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