IR2111SPBF - Infineon

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

IR2111SPBF
Manufacturer

Infineon
ChipWorker Part#

CW9945809
Category

FET Driver
Package

SOIC-8
Description

Infineon IR2111SPBF, Dual MOSFET Power Driver 0.5A Half Bridge, 10 → 20V, 8Pin SOIC
Documentation

Datasheet

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IR2111SPBF Specifications

Attribute	Attribute Value

Part Number	IR2111SPBF
Manufacturer	Infineon
ChipWorker Part#	CW9945809
Category	FET Driver
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	10.0V (min)
Power Rating	625 mW
Rise/Fall Time	80ns, 40ns
Number of Outputs	2 Output
Output Voltage	600 V
Output Current	250.500 mA
Number of Channels	2 Channel
Number of Positions	8 Position
Power Dissipation	625 mW
Rise Time	130 ns
Fall Time	65 ns
Fall Time (Max)	65 ns
Fall Time (Max)	130 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	625 mW
Supply Voltage	10V ~ 20V
Supply Voltage (Max)	20 V
Supply Voltage (Min)	10 V
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Size-Length	5 mm
Size-Width	4 mm
Size-Height	1.5 mm
Operating Temperature	-40℃ ~ 150℃ (TJ)
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The IR2111SPBF is a high voltage high speed power MOSFET and IGBT Half-bridge Driver with dependent high and low-side referenced output channels designed for half-bridge applications. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic input is compatible with standard CMOS outputs. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Internal dead-time is provided to avoid shoot-through in the output half-bridge. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600V.
Floating channel designed for bootstrap operation
Tolerant to negative transient voltage (dV/dt immune)
Under-voltage lockout for both channels
CMOS Schmitt-triggered inputs with pull-down
Matched propagation delay for both channels
Internally set dead-time
High-side output in phase with input

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