IR2301SPBF - Infineon

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

IR2301SPBF
Manufacturer

Infineon
ChipWorker Part#

CW10439572
Category

FET Driver
Package

SOIC-8
Description

MOSFET DRVR 600V 0.35A 2Out Hi/Lo Side Non-Inv 8Pin SOIC Tube
Documentation

Datasheet

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IR2301SPBF Specifications

Attribute	Attribute Value

Part Number	IR2301SPBF
Manufacturer	Infineon
ChipWorker Part#	CW10439572
Category	FET Driver
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	5.00V (min)
Rise/Fall Time	130ns, 50ns
Number of Outputs	2 Output
Output Voltage	620 V
Output Current	0.2 A
Number of Positions	8 Position
Power Dissipation	625 mW
Fall Time (Max)	80 ns
Fall Time (Max)	220 ns
Operating Temperature (Max)	150 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	625 mW
Supply Voltage	5V ~ 20V
Supply Voltage (Max)	20 V
Supply Voltage (Min)	5 V
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Size-Length	5 mm
Size-Width	4 mm
Size-Height	1.5 mm
Operating Temperature	-40℃ ~ 150℃ (TJ)
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The IR2301SPBF is a high voltage high speed power MOSFET and IGBT high and low Side Driver with independent high and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600V.
Floating channel designed for bootstrap operation
Tolerant to negative transient voltage (dV/dt immune)
Under-voltage lockout for both channels
Logic and power ground ±5V offset
Lower di/dt gate driver for better noise immunity
Outputs in phase with inputs

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