IRS2113SPBF - Infineon

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

IRS2113SPBF
Manufacturer

Infineon
ChipWorker Part#

CW8955371
Category

FET Driver
Package

SOIC-16
Description

Power MOSFET and IGBT Driver, Hi/Lo Side, 600V, 2A, 16Pin SOIC WB, Tube
Documentation

Datasheet

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IRS2113SPBF Specifications

Attribute	Attribute Value

Part Number	IRS2113SPBF
Manufacturer	Infineon
ChipWorker Part#	CW8955371
Category	FET Driver
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Supply Voltage (DC)	10.0V (min)
Power Rating	1.25 W
Rise/Fall Time	25ns, 17ns
Number of Outputs	2 Output
Output Voltage	600 V
Output Current	2.5 A
Number of Channels	2 Channel
Number of Positions	16 Position
Power Dissipation	1250 mW
Fall Time (Max)	25 ns
Fall Time (Max)	35 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1250 mW
Supply Voltage	10V ~ 20V
Supply Voltage (Max)	20 V
Supply Voltage (Min)	10 V
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Size-Length	10.5 mm
Size-Width	7.6 mm
Size-Height	2.35 mm
Operating Temperature	-40℃ ~ 150℃ (TJ)
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The IRS2113SPBF is a high voltage high speed power MOSFET and IGBT high and low Side Driver with independent high-side and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 500 or 600V.
Floating channel designed for bootstrap operation
Tolerant to negative transient voltage (dV/dt immune)
Under-voltage lockout for both channels
Logic and power ground ±5V offset
CMOS Schmitt-triggered inputs with pull-down
Cycle-by-cycle edge-triggered shutdown logic
Matched propagation delay for both channels
Outputs in phase with inputs

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