ISO7221MD - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

ISO7221MD
Manufacturer

TI
ChipWorker Part#

CW8362661
Category

Interface Isolator, Digital Isolator
Package

SOIC-8
Description

Digital Isolator Logic 2CH 150Mbps 8Pin SOIC Digital Isolator Logic 2CH 150Mbps 8Pin SOIC
Documentation

Datasheet

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ISO7221MD Specifications

Attribute	Attribute Value

Part Number	ISO7221MD
Manufacturer	TI
ChipWorker Part#	CW8362661
Category	Interface Isolator, Digital Isolator
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	3.30 V, 5.00 V
Rise/Fall Time	1 ns
Supply Current	12 mA
Number of Channels	2 Channel
Number of Positions	8 Position
Power Dissipation	390 mW
Data Rate	150 Mbps
Isolation Voltage	2500 Vrms
Thermal Shutdown	No
Fall Time (Max)	2 ns
Fall Time (Max)	2 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	390 mW
Supply Voltage	3V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	3 V
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Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

Product Description

The ISO7221MD is a dual-channel Digital Isolator to facilitate PCB layout, the channels are oriented in the same direction. It has a logic input and output buffer separated by TI"s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000 VPK per VDE. Used in conjunction with isolated power supplies, this device block high voltage and isolate grounds, as well as prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. A binary input signal is conditioned, translated to a balanced signal and then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output.
1ns Maximum low channel-to-channel output skew
1ns Maximum low pulse-width distortion (PWD)
1ns Typical at 150Mbps low jitter content
50kV/µs Typical transient immunity
4kV ESD Protection
High electromagnetic immunity (EMI)
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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