MC100EPT21DR2G - ON Semiconductor

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

MC100EPT21DR2G
Manufacturer

ON Semiconductor
ChipWorker Part#

CW19470296
Category

Voltage Level Translator IC
Package

SOIC-8
Description

ON SEMICONDUCTOR MC100EPT21DR2G Voltage Level Translator, 2Input, 1.4ns, 3V to 3.6V, SOIC-8
Documentation

Datasheet

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MC100EPT21DR2G Specifications

Attribute	Attribute Value

Part Number	MC100EPT21DR2G
Manufacturer	ON Semiconductor
ChipWorker Part#	CW19470296
Category	Voltage Level Translator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	3.00V (min)
Halogen Free Status	Halogen Free
Number of Circuits	1 Circuit
Number of Channels	1 Channel
Number of Positions	8 Position
Number of Bits	1 Bit
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of Output Channels	1 Channel
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	4.9 mm
Size-Width	3.9 mm
Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The MC100EPT21DR2G is a 3.3V differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator in 8 pin SOIC package. Because LVPECL (positive ECL), LVDS, positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8 lead SOIC package makes MC100EPT21DR2G ideal for applications which require the translation of a clock or data signal. The VBB output allows this device to be cap coupled in either single ended or differential input mode. VBB output is tied to D input and D is driven for a non inverting buffer or VBB output is tied to the D input and D is driven for an inverting buffer when single ended cap coupled. VBB output is connected through a resistor to each input pin when cap coupled differentially. If used the VBB pin should be bypassed to VCC via a 0.01µF capacitor. It is used in precision clock translation applications.
1.4ns typical propagation delay
Maximum frequency of 350MHz at TA = 25°C
LVPECL/LVDS/CML inputs, LVTTL/LVCMOS outputs
24mA TTL outputs
Operating range (VCC) from 3V to 3.6V with GND = 0V
Temperature compensation and VBB output
Power supply current of 17mA (outputs set to HIGH) and 21mA (outputs set to LOW)
Duty cycle skew of 50% and part to part skew of 500ps at TA = 25°C
Output rise/fall times (0.8V to 2V) of 600ps
Operating temperature range from -40°C to +85°C

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