MC100LVEL14DWR2G - ON Semiconductor

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

MC100LVEL14DWR2G
Manufacturer

ON Semiconductor
ChipWorker Part#

CW26186470
Category

Clock Buffer, Driver, PLL IC
Package

SOIC-20
Description

Clock Multiplexer 5Out 2IN 1:5 20Pin SOIC W T/R
Documentation

Datasheet

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MC100LVEL14DWR2G Specifications

Attribute	Attribute Value

Part Number	MC100LVEL14DWR2G
Manufacturer	ON Semiconductor
ChipWorker Part#	CW26186470
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	SOIC-20
Halogen Free Status	Halogen Free
Number of Outputs	5 Output
Number of Circuits	1 Circuit
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.8V
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Size-Length	12.95 mm
Size-Width	7.6 mm
Size-Height	2.4 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	EAR99

Product Description

The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of -3.0 V to -3.8 V ( or 3.0 V to 3.8 V). The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias AC coupled inputs. When used, decouple V via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
Features
---
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50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
ESD Protection: >2 KV HBM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -3.8 V
Internal Input Pulldown Resistors on CLK
Q Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Flammability Rating: UL-94 code V-0 @ 1/8",
Oxygen Index 28 to 34
Transistor Count = 303 devices

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