MC74VHCT125ADR2G - ON Semiconductor

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

MC74VHCT125ADR2G
Manufacturer

ON Semiconductor
ChipWorker Part#

CW21853171
Category

Logic Controller, Logic IC
Package

SOIC-14
Description

Buffer/Line Driver 4CH Non-Inverting 3-ST CMOS 14Pin SOIC N T/R
Documentation

Datasheet

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MC74VHCT125ADR2G Specifications

Attribute	Attribute Value

Part Number	MC74VHCT125ADR2G
Manufacturer	ON Semiconductor
ChipWorker Part#	CW21853171
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	SOIC-14
Supply Voltage (DC)	4.50V (min)
Halogen Free Status	Halogen Free
Number of Outputs	4 Output
Number of Circuits	4 Circuit
Number of Channels	4 Channel
Number of Positions	14 Position
Number of Bits	4 Bit
Power Dissipation	500 mW
Number of Inputs	4 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Power Dissipation (Max)	500 mW
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	8.75 mm
Size-Width	4 mm
Size-Height	1.5 mm
Operating Temperature	-55℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99

Product Description

The MC74VHCT125ADR2G is a quad Bus Buffer with 3-state control inputs. It is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent bipolar Schottky TTL while maintaining CMOS low power dissipation. It requires the 3-state control input (OE) to be set High to place the output into the high impedance state. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 to 5V, because it has full 5V CMOS level output swings. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion. The internal circuit is composed of 3-stage, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.
Power down protection provided on inputs
Balanced propagation delays
Pin and function compatible with other standard logic families
Designed for 2 to 5.5V operating range
High speed - Propagation delay (tpd) = 3.8ns typical at VCC = 5V
Low power dissipation - ICC = 4µA maximum at TA = 25°C
Latch-up performance exceeds 300mA
Chip complexity - 72 FETs or 18 equivalent gates

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