NB3N3020DTG - ON Semiconductor

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

NB3N3020DTG
Manufacturer

ON Semiconductor
ChipWorker Part#

CW19682640
Category

Clock Generator IC
Package

TSSOP-16
Description

Clock Generator 2MHz to 210MHz Input 210MHz Output 16Pin TSSOP Rail
Documentation

Datasheet

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NB3N3020DTG Specifications

Attribute	Attribute Value

Part Number	NB3N3020DTG
Manufacturer	ON Semiconductor
ChipWorker Part#	CW19682640
Category	Clock Generator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Frequency	210 MHz
Supply Voltage (DC)	2.97V (min)
Halogen Free Status	Halogen Free
Number of Outputs	2 Output
Output Current	25 mA
Supply Current	75 mA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Duty Cycle	50 %
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	40 ℃
Supply Voltage	2.97V ~ 3.63V
Supply Voltage (Max)	3.63 V
Supply Voltage (Min)	2.97 V
Input Voltage	3.3 V
	expand all
Size-Length	5.1 mm
Size-Width	4.5 mm
Size-Height	1.05 mm
Weight	0.0027678208248 kg
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The NB3N3020DTG is a low-phase noise selectable Clock Multiplier takes a 5 to 27MHz fundamental mode parallel resonant crystal or a 2 to 210MHz LVCMOS single ended clock source and generates a differential LVPECL output and a single ended LVCMOS/LVTTL output at a selectable clock output frequency which is a multiple of the input clock frequency. Three tri-level (low, mid, high) LVCMOS/LVTTL single ended select pins set one of 26 possible clock multipliers. The LVCMOS/LVTTL output enable (OE1) tri-states the LVCMOS/LVTTL clock output (CLK1) when low. When the LVTTL/LVCMOS output enable (OE2) is LOW, LVPECL CLK2 is forced LOW and LVPECL CLK2 is forced HIGH.
External loop filter is not required
LVPECL Differential output
LVCMOS/LVTTL outputs
RMS period jitter of 5ps

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