NB6N14SMNG - ON Semiconductor

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

NB6N14SMNG
Manufacturer

ON Semiconductor
ChipWorker Part#

CW5052115
Category

Clock Buffer, Driver, PLL IC
Package

QFN-16
Description

Clock Divider, Fanout Buffer IC, 2GHz, 4Outputs, LVDS, 3V to 3.6V, QFN-16
Documentation

Datasheet

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NB6N14SMNG Specifications

Attribute	Attribute Value

Part Number	NB6N14SMNG
Manufacturer	ON Semiconductor
ChipWorker Part#	CW5052115
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	QFN-16
Frequency	2 GHz
Supply Voltage (DC)	3.00V (min)
Halogen Free Status	Halogen Free
Number of Outputs	4 Output
Supply Current	65.0 mA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	3 mm
Size-Width	3 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	EAR99

Product Description

The NB6N14SMNG is a 3.3V 1:4 AnyLevel differential input to LVDS fan-out buffer/translator in 16 pin QFN package. This differential 1:4 clock or data receiver and will accept AnyLevel differential input signals, LVPECL, CML or LVDS. These signals will be translated to LVDS and four identical copies of clock or data will be distributed, operating up to 2GHz or 2.5Gb/s, respectively. As such, the NB6N14S is ideal for SONET, GigE, fibre channel, backplane and other clock or data distribution applications. It has a wide input common mode range from GND + 50mV to VCC - 50mV. Combined with the 50 ohm internal termination resistors at the inputs, the NB6N14S is ideal for translating a variety of differential or single ended clock or data signals to 350mV typical LVDS output levels.
Maximum input clock frequency > 2GHz
Maximum input data rate > 2.5Gb/s
1ps maximum RMS clock jitter
Typically 10ps data dependent jitter
380ps typical propagation delay
120ps typical rise and fall times
Vref_ac reference output
TIA/EIA - 644 compliant
Functionally compatible with existing 3.3V LVEL, LVEP, EP and SG devices

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