OMAPL138BZCE3 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

OMAPL138BZCE3
Manufacturer

TI
ChipWorker Part#

CW93748611
Category

Microprocessor IC
Package

NFBGA-361
Description

0-BIT, 50MHz, OTHER DSP, PBGA361, 13 X 13MM, 0.65MM PITCH, GREEN, PLASTIC, NFBGA-361
Documentation

Datasheet

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OMAPL138BZCE3 Specifications

Attribute	Attribute Value

Part Number	OMAPL138BZCE3
Manufacturer	TI
ChipWorker Part#	CW93748611
Category	Microprocessor IC
Documentation	Datasheet
Number of Pins	361 Pin
Case/Package	NFBGA-361
Frequency	456 MHz
Number of Positions	361 Position
Clock Speed	375456 MHz
RAM Memory Size	8 KB
Number of Bits	32 Bit
Number of UARTs	3 UART
Number of Inputs and Outputs	16 Input IO
Operating Temperature (Max)	90 ℃
Operating Temperature (Min)	0 ℃
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Size-Height	0.94 mm
Operating Temperature	0℃ ~ 90℃ (TJ)
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The OMAP-L1X series DSP+ARM® low-power Applications Processor based on an ARM926EJ-S and a C674x DSP core. This processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The dual-core architecture of the device provides benefits of both DSP and reduced instruction set computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32- or 16-bit instructions and processes 32-, 16- or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
375- and 456MHz ARM926EJ-S™ RISC MPU
ARM926EJ-S core - 32- and 16-bit (Thumb®) instructions and DSP instruction extensions
16kB Instruction cache and data cache
8kB RAM (vector table)
64kB ROM
C674x instruction set feature - Superset of the C67x+ and C64x+ ISAs
C674x two-level cache memory architecture
Enhanced direct memory access controller 3 (EDMA3)
TMS320C674x floating-point VLIW DSP core
Supports up to four SP additions per clock and four DP additions every two clocks
Two multiply functional units
Hardware support for modulo loop operation
Protected mode operation
Exceptions support for error detection and program redirection
Software support - TI DSP BIOS™, chip support library and DSP library
128kB RAM shared memory
Three configurable 16550-type UART modules
LCD controller
Two serial peripheral interfaces (SPIs) each with multiple chip selects
One host-port interface (HPI) with 16-bit-wide Muxed address and data bus for high bandwidth

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