PC16552DV - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

PC16552DV
Manufacturer

TI
ChipWorker Part#

CW25592068
Category

UART Chip, UART Interface IC
Package

PLCC-44
Description

UART 2CH 16Byte FIFO 5V 44Pin PLCC Tube
Documentation

Datasheet

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PC16552DV Specifications

Attribute	Attribute Value

Part Number	PC16552DV
Manufacturer	TI
ChipWorker Part#	CW25592068
Category	UART Chip, UART Interface IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	44 Pin
Case/Package	PLCC-44
Supply Voltage (DC)	5.00 V
Operating Voltage	5.00 V
Supply Current	30 mA
Number of Channels	2 Channel
Number of Positions	44 Position
Clock Speed	24.0 MHz
Power Dissipation	1000 mW
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Power Dissipation (Max)	1000 mW
Supply Voltage	5 V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Product Lifecycle Status	Active
Packaging	Tube
RoHS	Non-Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The PC16552DV is an Universal Asynchronous Receiver/Transmitter (UART) features that two serial channels are completely independent except for a common CPU interface and crystal input. On power-up both channels are functionally identical to the 16450. Each channel can operate with on-chip transmitter and receiver FIFOs (FIFO mode) to relieve the CPU of excessive software overhead. In FIFO mode each channel is capable of buffering 16 bytes (plus 3-bits of error data per byte in the RCVR FIFO) of data in both the transmitter and receiver. All the FIFO control logic is on-chip to minimize system overhead and maximize system efficiency. Signalling for DMA transfers is done through two pins per channel (TXRDY# and RXRDY#). The RXRDY# function is multiplexed on one pin with the OUT 2# and BAUDOUT functions. The CPU can select these functions through a new register (Alternate Function Register). Each channel performs serial-to-parallel conversion on data characters.
Dual independent UARTs
Capable of running all existing 16450 and PC16550D software
After reset, all registers are identical to the 16450 register set
Read and write cycle times of 84ns
Independently controlled transmit, receive, line status and data set interrupts
MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
Even, odd or no-parity bit generation and detection
False start bit detection
Complete status reporting capabilities
TRI-STATE® TTL drive for the data and control buses
Line-break generation and detection
Loopback controls for communications link fault isolation
Break, parity, overrun and framing-error simulation
Full prioritized interrupt system controls
Can also be reset to 16450 Mode under software control

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