PC48F4400P0VB00 - Intel

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

PC48F4400P0VB00
Manufacturer

Intel
ChipWorker Part#

CW446554004
RoHS

Lead free / RoHS Compliant
Description

Intel StrataFlash Embedded Memory
Documentation

Datasheet

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PC48F4400P0VB00 Specifications

Attribute	Attribute Value

Part Number	PC48F4400P0VB00
Manufacturer	Intel
ChipWorker Part#	CW446554004
Documentation	Datasheet
Case/Package	LBGA
	expand all
Product Lifecycle Status	Unknown
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	EAR99

Product Description

Introduction
This document provides information about the Intel StrataFlash® Embedded Memory (P30) device and describes its features, operation, and specifications.
Product Features
■ High performance
— 85/88 ns initial access
— 40 MHz with zero wait states, 20 ns clock-to data output synchronous-burst read mode
— 25 ns asynchronous-page read mode
— 4-, 8-, 16-, and continuous-word burst mode
— Buffered Enhanced Factory Programming (BEFP) at 5 µs/byte (Typ)
— 1.8 V buffered programming at 7 µs/byte (Typ)
■ Architecture
— Multi-Level Cell Technology: Highest Density at Lowest Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or bottom configuration
— 128-KByte main blocks
■ Voltage and Power
—VCC(core) voltage: 1.7 V – 2.0 V
—VCCQ (I/O) voltage: 1.7 V – 3.6 V
— Standby current: 55 µA (Typ) for 256-Mbit
— 4-Word synchronous read current: 13 mA (Typ) at 40 MHz
■ Quality and Reliability
— Operating temperature: –40 °C to +85 °C
• 1-Gbit in SCSP is –30 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (130 nm)
■ Security
— One-Time Programmable Registers:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OTP bits
— Selectable OTP Space in Main Array:
• 4x32KB parameter blocks + 3x128KB main blocks (top or bottom configuration)
— Absolute write protection: VPP= VSS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
■ Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
—Intel® Flash Data Integrator optimized
— Basic Command Set and Extended Command Set compatible
— Common Flash Interface capable
■ Density and Packaging
— 64/128/256-Mbit densities in 56-Lead TSOP package
— 64/128/256/512-Mbit densities in 64-Ball Intel®Easy BGA package
— 64/128/256/512-Mbit and 1-Gbit densities in Intel®QUAD+ SCSP
— 16-bit wide data bus

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