PCA9511ADP - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

PCA9511ADP
Manufacturer

NXP
ChipWorker Part#

CW47303366
Category

Logic Controller, Logic IC
Package

TSSOP
Description

I2C Buffer 3.3V/5V 8Pin TSSOP
Documentation

Datasheet

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PCA9511ADP Specifications

Attribute	Attribute Value

Part Number	PCA9511ADP
Manufacturer	NXP
ChipWorker Part#	CW47303366
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	TSSOP
Supply Voltage (DC)	2.70V (min)
Number of Positions	8 Position
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.7V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2.7 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
HK STC License	NLR

Product Description

The PCA9511ADP is a hot swappable I²C-bus and SMBus Buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, this provides bidirectional buffering, keeping the backplane and card capacitances isolated. Its rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. It incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW and an open-drain READY output pin, which indicates that the backplane and card sides are connected together or not. During insertion, buffer SDA and SCL lines are pre-charged to 1V to minimize the current required to charge the parasitic capacitance of the chip.
Compatible with I²C-bus Standard-mode, I²C-bus Fast-mode and SMBus standards
Active HIGH ENABLE input
Active HIGH READY open-drain output
Supporting clock stretching and multiple master arbitration/synchronization
Built-in ∆V/∆t rise time accelerators
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100mA
0Hz to 400kHz Clock frequency

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