PCA9615DPJ - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

PCA9615DPJ
Manufacturer

NXP
ChipWorker Part#

CW7953928
Category

Interface IC, Interface Controller
Package

TSSOP-10
Description

I2C Buffer 2.5V/3.3V/5V 10Pin TSSOP T/R
Documentation

Datasheet

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PCA9615DPJ Specifications

Attribute	Attribute Value

Part Number	PCA9615DPJ
Manufacturer	NXP
ChipWorker Part#	CW7953928
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	10 Pin
Case/Package	TSSOP-10
Supply Current	16 µA
Number of Channels	2 Channel
Number of Positions	10 Position
Power Dissipation	100 mW
Input Capacitance	7 pF
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	100 mW
Supply Voltage	2.3V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2.3 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	EAR99

Product Description

Overview
The PCA9615 is a Fast-mode Plus (Fm+) SMBus/I²C-bus buffer that extends the normal single-ended SMBus/I²C-bus through electrically noisy environments using a differential SMBus/I²C-bus (dI²C) physical layer, which is transparent to the SMBus/I²C-bus protocol layer. It consists of two single-ended to differential driver channels for the SCL (serial clock) and SDA (serial data).
The use of differential transmission lines between identical dI²C bus buffers removes electrical noise and common-mode offsets that are present when signal lines must pass between different voltage domains, are bundled with hostile signals, or run adjacent to electrical noise sources, such as high energy power supplies and electric motors.
The SMBus/I²C-bus was conceived as a simple slow speed digital link for short runs, typically on a single PCB or between adjacent PCBs with a common ground connection. Applications that extend the bus length or run long cables require careful design to preserve noise margin and reject interference.
The dI²C-bus buffers were designed to solve these problems and are ideally suited for rugged high noise environments and/or longer cable applications, allow multiple slaves, and operate at bus speeds up to 1 MHz clock rate. Cables can be extended to at least 3 meters (3 m), or longer cable runs at lower clock speeds. The dI²C-bus buffers are compatible with existing SMBus/I²C-bus devices and can drive Standard, Fast-mode, and Fast-mode Plus devices on the single-ended side.
Signal direction is automatic, and requires no external control. To prevent bus latch up, the standard SMBus/I²C-bus side of the bus buffer, the PCA9615 employs static offset, care should be taken when connecting these to other SMBus/I²C-bus buffers that may not operate with offset.
This device is a bridge between the normal 2-wire single-ended wired-OR SMBus/I²C-bus and the 4-wire dI²C-bus.
Additional circuitry allows the PCA9615 to be used for ‘hot swap’ applications, where systems are always on, but require insertion or removal of modules or cards without disruption to existing signals.
The PCA9615 has two supply voltages, VDD(A) and VDD(B). VDD(A), the card side supply, only serves as a reference and ranges from 2.3 V to 5.5 V. VDD(B), the line side supply, serves as the majority supply for circuitry and ranges from 3.0 V to 5.5 V.
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## Features
* New dI²C-bus buffers offer improved resistance to system noise and ground offset up to 1⁄2 of supply voltage
* 2 channel dI²C (differential I²C-bus) to Fm+ single-ended buffer operating up to 1 MHz with 30 mA SDA/SCL drive capability
* Hot swap (allows insertion or removal of modules or card without disruption to bus data)
* EN signal (PCA9615 input) controls PCA9615 hot swap sequence
* Bus idle detect (PCA9615 internal function) waits for a bus idle condition before connection is made
* Compatible with I²C-bus Standard/Fast-mode and SMBus, Fast-mode Plus up to 1 MHz
* Single-ended I²C-bus on card side up to 540 pF
* Differential I²C-bus on cable side supporting multi-drop bus
* Maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency)
* dI²C output: 1.5 V differential output with nominal terminals
* Differential line impedance (user defined): 100 Ω nominal suggested
* Receive input sensitivity: ±200 mV
* Hysteresis: ±30 mV typical
* Input impedance: high-impedance (200 kΩ typical)
* Receive input voltage range: ‑0.5 V to +5.5 V
* Lock-up free operation
* Supports arbitration and clock stretching across the dI²C-bus buffers
* Powered-off and powering-up high-impedance I²C-bus pins
* Operating supply voltage (VDD(A)) range of 2.3 V to 5.5 V with single-ended side 5.5 V tolerant
* Differential I²C-bus operating supply voltage (VDD(B)) range of 3.0 V to 5.5 V with 5.5 V tolerant. Best operation is at 5 V.
* ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
* Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
* Package offering: TSSOP10
## Target Applications
* Monitor remote temperature/leak detectors in harsh environment
* Control of power supplies in high noise environment
* Transmission of I²C-bus between equipment cabinets
* Commercial lighting and industrial heating/cooling control
* Any application that requires long I²C-bus runs in electrically noisy environments
* Any application with multiple power suppliers and the potential for ground offsets up to 2.5 V
## Features

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