PCA9641PWJ - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

PCA9641PWJ
Manufacturer

NXP
ChipWorker Part#

CW4712604
Category

Interface IC, Interface Controller
Package

TSSOP-16
Description

PCA9641 - 2Channel I2C-bus master arbiter TSSOP 16Pin
Documentation

Datasheet

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PCA9641PWJ Specifications

Attribute	Attribute Value

Part Number	PCA9641PWJ
Manufacturer	NXP
ChipWorker Part#	CW4712604
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Current	100 mA
Number of Channels	2 Channel
Number of Positions	16 Position
Input Capacitance	6 pF
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.3 V
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Weight	84.460615 mg
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free

Product Description

Overview
The PCA9641 is a 2-to-1 I²C master demultiplexer with an arbiter function. It is designed for high reliability dual master I²C-bus applications where correct system operation is required, even when two I²C-bus masters issue their commands at the same time. The arbiter will select a winner and let it work uninterrupted, and the losing master will take control of the I²C-bus after the winner has finished. The arbiter also allows for queued requests where a master requests the downstream bus while the other master has control.
A race condition occurs when two masters try to access the downstream I²C-bus at almost the same time. The PCA9641 intelligently selects one winning master and the losing master gains control of the bus after the winning master gives up the bus or the reserve time has expired.
Multiple transactions can be done without interruption. The time needed for multiple transactions on the downstream bus can be reserved by programming the Reserve Time register. During the reserve time, the downstream bus cannot be lost.
Software reset allows a master to send a reset through the I²C-bus to put the PCA9641’s registers into the power-on reset condition.
The Device ID of the PCA9641 can be read by the master and includes manufacturer, device type and revision.
When there is no activity on the downstream I²C-bus over 100 ms, optionally the PCA9641 will disconnect the downstream bus to both masters to avoid a lock-up on the I²C-bus.
The interrupt outputs are used to provide an indication of which master has control of the bus, and which master has lost the downstream bus. One interrupt input (INT_IN) collects downstream information and propagates it to the two upstream I²C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the master know if the shared mail box has any new mail or if the outgoing mail has not been read by the other master. Those interrupts can be disabled and will not generate an interrupt if the masking option is set.
The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage, which will be passed by the PCA9641. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate with 3.3 V devices without any additional protection.
The PCA9641 does not isolate the capacitive loading on either side of the device, so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels.
External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 3.6 V tolerant.
An active LOW reset input allows the PCA9641A to be initialized. Pulling the RESET pin LOW resets the I²C-bus state machine and configures the device to its default state as does the internal Power-On Reset (POR) function.
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## Features
* 2-to-1 bidirectional master selector
* Channel selection via I²C-bus
* I²C-bus interface logic; compatible with SMBus standards
* 2 active LOW interrupt outputs to master controllers
* Active LOW reset input
* Software reset
* Four address pins allowing up to 112 different addresses
* Arbitration active when two masters try to take the downstream I²C-bus at the same time
* The winning master controls the downstream bus until it is done, as long as it is within the reserve time
* Bus time-out after 100 ms on an inactive downstream I²C-bus (optional)
* Readable device ID (manufacturer, device type, and revision)
* Bus initialization/recovery function
* Low Ron switches
* Allows voltage level translation between 1.8 V, 2.3 V, 2.5 V, 3.3 V and 3.6 V buses
* No glitch on power-up
* Supports hot insertion
* Software identical for both masters
* Operating power supply voltage range of 2.3 V to 3.6 V
* All I/O pins are 3.6 V tolerant
* Up to 1 MHz clock frequency
* ESD protection exceeds 6000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
* Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
* Packages offered: TSSOP16, HVQFN16
## Target Applications
* High reliability systems with dual masters
* Gatekeeper multiplexer on long single bus
* Bus initialization/recovery for slave devices without hardware reset
* Allows masters without arbitration logic to share resources
## Features

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