PCA9698BS ,Interface IC, Interface Controller - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

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24 points

Part No

PCA9698BS
Manufacturer

NXP
ChipWorker Part#

CW183353069
Category

Interface IC, Interface Controller
Package

HVQFN
Description

NXP PCA9698BS I/O Expander, 40Bit, 1MHz, I2C, SMBus, 2.3V, 5.5V, HVQFN
Documentation

Datasheet
Ships from

Moscow
Наличие

224 pcs In Stock
Estimated Price

$ 2.86

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PCA9698BS Specifications

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Attribute	Attribute Value

Part Number	PCA9698BS
Manufacturer	NXP
ChipWorker Part#	CW183353069
Category	Interface IC, Interface Controller
Documentation	Datasheet
Number of Pins	56 Pin
Case/Package	HVQFN
Supply Voltage (DC)	2.30V (min)
Number of Positions	56 Position
Number of Inputs and Outputs	40 Input IO
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2.3 V
	expand all
Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

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Product Description

The PCA9698BS is a 40-bit parallel input/output Expander for I²C-bus applications organized in 5 banks of 8 I/Os. At 5V supply voltage, the outputs are capable of sourcing 10mA and sinking 25mA with a total package load of 1A to allow direct driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output. The PCA9698 is the first GPIO device in a new Fast-mode Plus (Fm+) family. Fm+ device offers higher frequency (up to 1MHz) and longer, more densely populated bus operation (up to 4000pF). The device is fully configurable: output ports can be programmed to be totem-pole or open-drain and logic states can change at either the acknowledge (bank change) or the stop command (global change), each input port can be masked to prevent it from generating interrupts when its state changes, I/O data logic state can be inverted when read by the system master.
Low standby current consumption
Readable device ID
Minimize line disturbance
Signal transient rejection
Polarity inverter register allows inversion of the polarity of the I/O pins when read
Active low output enable (OE) input pin 3-states all outputs
40 Configurable I/O pins that default to inputs at power-up
64 Programmable slave addresses using 3 address pins
Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA

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