PCAL6524HEAZ - NXP
The pictures are for reference only, and the specific specifications can be found in the product manual.
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PCAL6524HEAZ Specifications
| Attribute | Attribute Value |
|---|---|
| Part Number | PCAL6524HEAZ |
| Manufacturer | NXP |
| ChipWorker Part# | CW22790866 |
| Category | Interface IC, Interface Controller |
| Documentation | Datasheet |
| 3D Model | 3D Model |
| Mounting Style | Surface Mount |
| Number of Pins | 32 Pin |
| Case/Package | HUQFN-32 |
| Supply Voltage (DC) | 5.50V (max) |
| Number of Positions | 32 Position |
| Clock Speed | 1 MHz |
| Number of Inputs and Outputs | 24 Input IO |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 1.65V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| expand all | |
| Operating Temperature | -40℃ ~ 85℃ |
| Product Lifecycle Status | Unknown |
| Packaging | Cut Tape (CT) |
| RoHS | RoHS Compliant |
| Lead-Free Status | Lead Free |
| REACH SVHC Compliance Edition | 2015/12/17 |
Product Description
- Overview
- The PCAL6524 is a 24-bit general purpose I/O expander that provides remote I/O expansion for most microcontroller families via the Fast-mode Plus (Fm+) I²C-bus interface. The ultra low-voltage interface allows for direct connection to a microcontroller operating down to 0.8 V.
- NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level down to 0.8 V to I/O devices operating at a different voltage level 1.65 V to 5.5 V. The PCAL6524 has built-in level shifting feature that makes these devices extremely flexible in mixed power supply systems where communication between incompatible I/O voltages is required, allowing seamless communications with next-generation low voltage microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.
- There are two supply voltages for PCAL6524: VDD(I2C-bus) and VDD(P). VDD(I2C-bus) provides the supply voltage for the interface at the master side (for example, a microcontroller) and the VDD(P) provides the supply for core circuits and Port P. The bidirectional voltage level translation in the PCAL6524 is provided through VDD(I2C-bus). VDD(I2C-bus) should be connected to the VDD of the external SCL/SDA lines. This indicates the VDD level of the I²C-bus to the PCAL6524, while the voltage level on Port P of the PCAL6524 is determined by the VDD(P).
- The PCAL6524 fully meets the Fm+ I²C-bus specification at speeds to 1 MHz and implements Agile I/O, which are additional features specifically designed to enhance the I/O. These additional features are: programmable output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs.
- Additional Agile I/O Plus features include I²C software reset and device ID. Interrupts can be specified by level or edge, and can be cleared individually without disturbing the other interrupt events. Also, switch debounce hardware is implemented.
- At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register, saving external logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete components.
- The power-on reset puts the registers in their default state and initializes the I²C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part. The system master can also accomplish a reset via an I²C command and initialize all registers to their default state.
- The PCAL6524 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state. As well, the INT output can be specified to activate on input pin edges. There are a large number of interrupt mask functions available to maximize flexibility.
- INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without communication via the I²C-bus. Thus, the PCAL6524 can remain a simple slave device. The input latch feature holds or latches the input pin state and keeps the logic values that created the interrupt until the master can service the interrupt. This minimizes the host’s interrupt service response for fast moving inputs.
- The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current.
- One hardware pin (ADDR) can be used to program and vary the fixed I²C-bus address and allow up to four devices to share the same I²C-bus or SMBus.
- MoreLess
- ## Features
- * I²C-bus to parallel port expander
- * 1 MHz Fast-mode Plus I²C-bus
- * Operating power supply voltage range of 0.8 V to 3.6 V on the I²C-bus side
- * Allows bidirectional voltage-level translation and GPIO expansion between 0.8 V to 3.6 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V, 5.5 V Port P
- * Low standby current consumption: 2.0 µA typical at 3.3 V VDD(P)
- * Schmitt trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs:
- * Vhys = 0.05 V (typical) at 0.8 V
- * Vhys = 0.18 V (typical) at 1.8 V
- * Vhys = 0.33 V (typical) at 3.3 V
- * 5.5 V tolerant I/O ports and 3.6 V tolerant I²C-bus pins
- * Active LOW reset input (RESET)
- * Open-drain active LOW interrupt output (INT)
- * Internal power-on reset
- * Noise filter on SCL/SDA inputs
- * Latched outputs with 25 mA drive maximum capability for directly driving LEDs
- * Latch-up performance exceeds 100 mA per JESD 78, Class II
- * ESD protection exceeds JESD 22:
- * 2000 V Human-Body Model (A114-A)
- * 1000 V Charged-Device Model (C101)
- * Packages offered: TSSOP32, HUQFN32, VFBGA36
- ### Agile I/O features
- * Output port configuration: bank selectable or pin selectable push-pull or open-drain output stages
- * Interrupt status: read-only register identifies the source of an interrupt
- * Bit-wise I/O programming features:
- * Output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance applications
- * Input latch: Input Port register values changes are kept until the Input Port register is read
- * Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable
- * Pull-up/pull-down selection: 100 kΩ pull-up/pull-down resistor selection
- * Interrupt mask: mask prevents the generation of the interrupt when input changes state to prevent spurious interrupts
- ### Additional Agile I/O Plus featu
- * Interrupt edge specification on a bit-by-bit basis
- * Interrupt individual clear without disturbing other events
- * Read all interrupt events without clear
- * Switch debounce hardware
- * General call software reset
- * I²C software Device ID function
- ## Features
- * I²C software Device ID function
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