PCI2040PGE - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

PCI2040PGE
Manufacturer

TI
ChipWorker Part#

CW7194944
Category

Interface IC, Interface Controller
Package

LQFP-144
Description

PCI Bridge Chip 32Bit 33MHz 32Bit 144Pin LQFP Tray
Documentation

Datasheet

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PCI2040PGE Specifications

Attribute	Attribute Value

Part Number	PCI2040PGE
Manufacturer	TI
ChipWorker Part#	CW7194944
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	144 Pin
Case/Package	LQFP-144
Supply Voltage (DC)	3.30 V, 5.00 V
Clock Speed	33.0 MHz
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	3.3V, 5V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	3 V
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Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

The TI PCI2040 is a PCI-DSP bridge that provides a glueless connection between the 8-bit host port interface (HPI) port on the TMS320C54X or the 16-bit HPI port on TMS320C6X to the high performance PCI bus. It provides a PCI bus target interface compliant with the _PCI Local Bus Specification_.
The PCI2040 provides several external interfaces: the PCI bus interface with compact PCI support, the HPI port interface with support for up to four DSPs, a serial ROM interface, a general-purpose input/output interface (GPIOs), and a 16-bit general-purpose bus to provide a glueless interface to TI JTAG test bus controller (TBC). The PCI2040 universal target-only PCI interface is compatible with 3.3-V to 5-V signaling environments.
The PCI2040 interfaces with DSPs via a data bus (HPI port). The PCI2040 also provides a serial ROM interface for preloading several registers including the subsystem ID and subsystem vendor ID.
The PCI2040, compliant with the latest _PCI Bus Power Management Interface Specification_, provides serveral low-power features that reduce power consumption. Furthermore, an advanced CMOS process achieves low system power consumption.
Unused PCI2040 inputs mus be pulled to a valid logic level using a pullup resistor.

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