PCI4510 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

PCI4510
Manufacturer

TI
ChipWorker Part#

CW435556041
Package

BGA
Description

PC Card and Integrated Two-Port PHY/Link Layer Controller
Documentation

Datasheet

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PCI4510 Specifications

Attribute	Attribute Value

Part Number	PCI4510
Manufacturer	TI
ChipWorker Part#	CW435556041
Documentation	Datasheet
Mounting Style	Surface Mount
Case/Package	BGA
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Product Lifecycle Status
RoHS	RoHS Compliant
Lead-Free Status	Lead Free

Product Description

The Texas Instruments PCI4510 device is an integrated single-socket PC Card controller with an IEEE 1394 open host controller link-layer controller (LLC) and two-port 1394 PHY. This high performance integrated solution provides the latest in both PC Card and IEEE 1394 technology.
The Texas Instruments PCI4510 device is compliant with _PCI Local Bus Specification_. Function 0 provides the independent PC Card socket controller compliant with the latest _PC Card Standards_. The PCI4510 device provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports either 16-bit or CardBus PC Cards in the socket, powered at 5 V or 3.3 V, as required.
There are no PCMCIA card and socket service software changes required to move systems from the existing CardBus socket controller to the PCI4510 device. The PCI4510 device is register compatible with the Intel 82365SLDF ExCA controller and implements the host interface defined in the _PC Card Standard_. The PCI4510 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and the pipeline architecture provides an unsurpassed performance level with sustained bursting. The PCI4510 device can be programmed to accept posted writes to improve bus utilization. All card signals are internally buffered to allow hot insertion and removal without external buffering.
Function 1 of the PCI4510 device is an integrated IEEE 1394a-2000 open host controller interface (OHCI) PHY/link-layer controller (LLC) device that is fully compliant with the _PCI Local Bus Specification_, the _PCI Bus Power Management Interface Specification_, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the _1394 Open Host Controller Interface Specification_. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The PCI4510 device provides two 1394 ports that have separate cable bias (TPBIAS). The PCI4510 device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.
As required by the _1394 Open Host Controller Interface Specification_ and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the PCI4510 device is compliant with the _PCI Bus Power Management Interface Specification_ as specified by the _PC 2001 Design Guide_ requirements. The PCI4510 device supports the D0, D1, D2, and D3 power states.
The PCI4510 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the IEEE 1394 data.
The PCI4510 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The PCI4510 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers.
The PCI4510 PHY-layer provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission.
The PCI4510 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data. Data bits to be transmitted through the cable ports are received from the integrated LLC and are latched internally in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the twisted-pair B (TPB) cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair A (TPA) cable pair(s).
Various implementation-specific functions and general-purpose inputs and outputs are provided through several multifunction terminals. These terminals present a system with options, such as PCI LOCK\ and parallel IRQs. ACPI-complaint general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs.
The PCI4510 device is compliant with the latest _PCI Bus Power Management Specification_, and provides several low-power modes, which enable the host power system to further reduce power consumption. The PCI4510 device also has a four-pin interface compatible with both the TI TPS2211A and TPS2221 power switches.
An advanced CMOS process achieves low power consumption and allows the PCI4510 device to operate at PCI clock rates up to 33 MHz.
_PC Card Standard_ 8.0 compliant
_PCI Bus Power Management Interface Specification_ 1.1 compliant
_Advanced Configuration and Power Interface Specification_ 2.0 compliant
_PCI Local Bus Specification Revision 2.2_ compliant
PC 98/99 and PC2001 compliant
Compliant with the _PCI Bus Interface Specification_ for PCI-to-CardBus Bridges
Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std 1394a-2000
Fully compliant with _1394 Open Host Controller Interface Specification_ 1.1
Compatible with both TPS2211A and TPS2221 PC Card power switches
1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core VCC
Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Supports PC Card or CardBus with hot insertion and removal
Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
Supports serialized IRQ with PCI interrupts
Programmable multifunction terminals
Serial ROM interface for loading subsystem ID and subsystem vendor ID
ExCA-compatible registers are mapped in memory or I/O space
Intel 82365SLDF register compatible
Supports ring indicate, SUSPEND\, PCI CCLKRUN\ protocol, and PCI bus lock (LOCK)\
Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals
Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
Compliant with _Intel Mobile Power Guideline 2000_
Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer and inactive ports powered down, ultralow-power sleep mode
Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
Cable ports monitor line conditions for active connection to remote node
Cable power presence monitoring
Separate cable bias (TPBIAS) for each port
Physical write posting of up to three outstanding transactions
PCI burst transfers and deep FIFOs to tolerate large host latency
External cycle timer control for customized synchronization
Extended resume signaling for compatibility with legacy DV components
PHY-Link logic performs system initialization and arbitration functions
PHY-Link encode and decode functions included for data-strobe bit level encoding
PHY-Link incoming data resynchronized to local clock
Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s
Node power class information signaling for system power management
Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features
Isochronous receive dual-buffer mode
Out-of-order pipelining for asynchronous transmit requests
Register access fail interrupt when the PHY SCLK is not active
PCI power-management D0, D1, D2, and D3 power states
Initial bandwidth available and initial channels available registers
PME\ support per _1394 Open Host Controller Interface Specification_
Advanced submicron, low-power CMOS technology
FireWire is a trademark of Apple Computer, Inc..
i.LINK is a trademark of Sony Corporation of America..

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