PTN3363BSMP - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

PTN3363BSMP
Manufacturer

NXP
ChipWorker Part#

CW28996400
Category

Interface IC, Interface Controller
Package

HVQFN-32
Description

level shifter -40℃ to 105℃ 32Pin HVQFN EP T/R
Documentation

Datasheet

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PTN3363BSMP Specifications

Attribute	Attribute Value

Part Number	PTN3363BSMP
Manufacturer	NXP
ChipWorker Part#	CW28996400
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	32 Pin
Case/Package	HVQFN-32
Number of Positions	32 Position
Power Dissipation	72 mW
Number of Inputs	4 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3.3 V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.8 V
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Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free

Product Description

Overview
PTN3363 is a low power, high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain current-steering differential output signals, up to 3.4 Gbit/s per lane to support 36-bit deep color mode, 4K x 2K video format or 3D video data transport. Each of these lanes provides a level-shifting differential active buffer, with built-in Equalization, to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50  to 3.3 V on the sink side. Additionally, the PTN3363 provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel with active buffering and level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using active I²C-bus buffer technology providing redriving and level shifting as well as disablement (isolation between source and sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3363 typically come from a display source with multi-mode I/O, which supports multiple display standards, for example, DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.4b specification. By using PTN3363, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low.
The PTN3363 main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.2a and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The I²C-bus channel actively buffers as well as level-translates the DDC signals. The PTN3363 supports standby mode in order to minimize current consumption when Hot Plug Detect signal HPD_SINK is LOW.
PTN3363 is powered from a single 3.3 V power supply consuming a small amount of power (72 mW typical) and is offered in a 32-terminal HVQFN32 package.
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## Features
### High-speed TMDS level shifting
* Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain current-steering differential output signals
* TMDS level shifting operation up to 3.4 Gbit/s per lane (340 MHz TMDS clock) supporting 4K × 2K 3 Gbit/s and 3D video formats
* Programmable receive equalization
* Integrated 50 Ω termination resistors for self-biasing differential inputs
* Programmable high-impedance termination resistors for HDMI re-driver usage with external 50 Ω termination resistors
* Back-current safe outputs to disallow current when device power is off and monitor is on
* Disable feature to turn off TMDS inputs and outputs and to enter low‑power condition
* Selectable differential output termination on TMDS channels
### DDC level shifting
* Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side and vice versa)
* Rise time accelerator on connector side DDC ports
* Up to 400 kHz I²C-bus clock frequency
* Back-power safe sink-side terminals to disallow backdrive current when power is off or when DDC is not enabled
### HPD level shifting
* HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or from 5 V on the sink side to 3.3 V on the source side
* Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when no display is plugged in
* Back-power safe design on HPD_SINK to disallow backdrive current when power is off
### HDMI dongle detection support
* Incorporates I²C-bus slave ROM
* Responds to DDC read to address 81h
* Feature enabled by pins DDET and DDC_EN (must be enabled for correct operation in accordance with DisplayPort interoperability guideline)
### General
* Power supply 2.8 V to 3.6 V
* ESD resilience to 8 kV HBM, 1 kV CDM
* Power-saving modes
* Back-current-safe design on all sink-side main link, DDC and HPD terminals
* Transparent operation: no retiming or software configuration required
* 32-terminal HVQFN32 package
## Target Applications
* PC motherboard/graphics card
* Docking station
* DisplayPort to HDMI adapters supporting 4K x 2K and 3D video formats
* DisplayPort to DVI adapters required to drive long cables
## Features

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