S25FL128SAGMFI011 - Cypress Semiconductor

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

S25FL128SAGMFI011
Manufacturer

Cypress Semiconductor
ChipWorker Part#

CW4357473
Category

Flash Memory, Flash
Package

SOIC-16
Description

NOR Flash Serial (SPI, Dual SPI, Quad SPI) 3V/3.3V 128M-bit 128M/64M/32M x 1/2Bit/4Bit 8ns 16Pin SOIC W Tube
Documentation

Datasheet

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S25FL128SAGMFI011 Specifications

Attribute	Attribute Value

Part Number	S25FL128SAGMFI011
Manufacturer	Cypress Semiconductor
ChipWorker Part#	CW4357473
Category	Flash Memory, Flash
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Supply Voltage (DC)	2.70V (min)
Number of Positions	16 Position
Clock Speed	133 MHz
Memory Size	16000000 B
Access Time(Max)	8 ns
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.7V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.7 V
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Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Unknown
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	3A991.b.1.a

Product Description

The S25FL128SAGMFI011 is a 128MB MirrorBit® Flash Non-Volatile Memory CMOS 3V core with versatile I/O serial peripheral interface with multi-I/O. This family of devices connects to a host system via a serial peripheral interface (SPI). In addition, the FL-S family adds support for double Data rate read commands for SIO, DIO and QIO that transfer address and read data on both edges of the clock. The eclipse architecture features a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates supported with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically.

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