SMJ320C6415DGADW60 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SMJ320C6415DGADW60
Manufacturer

TI
ChipWorker Part#

CW393084371
Category

DSP, Digital Signal Processor
Package

FCPGA
Description

DSP Fixed-Point 32Bit 600MHz 4800MIPS 570Pin FCPGA Tray
Documentation

Datasheet

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SMJ320C6415DGADW60 Specifications

Attribute	Attribute Value

Part Number	SMJ320C6415DGADW60
Manufacturer	TI
ChipWorker Part#	CW393084371
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	570 Pin
Case/Package	FCPGA
Frequency	600 MHz
Clock Speed	600 MHz
Operating Temperature (Max)	115 ℃
Operating Temperature (Min)	-55 ℃
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Product Lifecycle Status	Active
Packaging	Tray
RoHS	Non-Compliant
Lead-Free Status	Contains Lead
Mil-Spec	Yes
ECCN Code	3A991.a.2
HK STC License	NLR

Product Description

* Highest-Performance Fixed-Point Digital Signal Processors (DSPs) * 2-, 1.67-, 1.39-ns Instruction Cycle Time * 600-MHz Clock Rate * Eight 32-Bit Instructions/Cycle * Twenty-Eight Operations/Cycle * 4800 MIPS * Fully Software-Compatible With C62x™ * C6414/15/16 Devices Pin-Compatible * VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core * Eight Highly Independent Functional Units With VelociTI.2™ Extensions: * Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle * Two Multipliers SupportFour 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle * Non-Aligned Load-Store Architecture * 64 32-Bit General-Purpose Registers * Instruction Packing Reduces Code Size * All Instructions Conditional * Instruction Set Features * Byte-Addressable (8-/16-/32-/64-Bit Data) * 8-Bit Overflow Protection * Bit-Field Extract, Set, Clear * Normalization, Saturation, Bit-Counting * VelociTI.2™ Increased Orthogonality * Viterbi Decoder Coprocessor (VCP) [C6416] * Supports Over 500 7.95-Kbps AMR * Programmable Code Parameters * Turbo Decoder Coprocessor (TCP) [C6416] * Supports up to Six 2-Mbps 3GPP (6 Iterations) * Programmable Turbo Code and Decoding Parameters * L1/L2 Memory Architecture * 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) * 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) * 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation) * Two External Memory Interfaces (EMIFs) * One 64-Bit (EMIFA), One 16-Bit (EMIFB) * Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) * 1280M-Byte Total Addressable External Memory Space * Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) * Host-Port Interface (HPI) * User-Configurable Bus Width (32-/16-Bit) * 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ] * Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O * Four-Wire Serial EEPROM Interface * PCI Interrupt Request Under DSP Program Control * DSP Interrupt Via PCI I/O Cycle * Three Multichannel Buffered Serial Ports * Direct Interface to T1/E1, MVIP, SCSA Framers * Up to 256 Channels Each * ST-Bus-Switching-, AC97-Compatible * Serial Peripheral Interface (SPI) Compatible (Motorola™) * Three 32-Bit General-Purpose Timers * Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416] * UTOPIA Level 2 Slave ATM Controller * 8-Bit Transmit and Receive Operations up to 50 MHz per Direction * User-Defined Cell Format up to 64 Bytes * Sixteen General-Purpose I/O (GPIO) Pins * Flexible PLL Clock Generator * IEEE-1149.1 (JTAG) Boundary-Scan-Compatible * 570-Pin Grid Array (PGA) Package (GAD Suffix) * 0.13-µm/6-Level Cu Metal Process (CMOS) * 3.3-V I/Os, 1.4-V Internal

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