SN65LVDM180D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDM180D
Manufacturer

TI
ChipWorker Part#

CW13799644
Category

Interface IC, Interface Controller
Package

SOIC-14
Description

M-LVDS PHY (<500Mbps) Full-Duplex LVDM Transceiver LVDS Transceiver 500Mbps 0.454V 14Pin SOIC Tube
Documentation

Datasheet

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SN65LVDM180D Specifications

Attribute	Attribute Value

Part Number	SN65LVDM180D
Manufacturer	TI
ChipWorker Part#	CW13799644
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	SOIC-14
Supply Voltage (DC)	3.00V (min)
Supply Current	15 mA
Power Dissipation	987 W
Data Rate	500 Mbps
Input Current (Min)	20 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	987 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

Product Description

The SN65LVDM180D is a differential Line Driver and Receiver uses low-voltage differential signaling (LVDS) to achieve high signaling rate. This circuit is similar to TIA/EIA-644 standard compliant device (SN65LVDS) counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247mV across a 50R load simulating two transmission lines in parallel. This allows having data buses with more than one driver or with two line termination resistors. The receiver detects a voltage difference of 50mV with up to 1V of ground potential difference between a transmitter and receiver. The intended application of these devices and signaling techniques is point-to-point half duplex, baseband data transmission over a controlled impedance media of approximately 100R characteristic impedance. The transmission media may be printed-circuit board traces, backplanes or cables.
Receiver has open-circuit failsafe design
Typical full-duplex signalling rate of 100Mbps
Bus-terminal ESD exceeds 12kV
Low-voltage differential signaling with typical output voltages of 340mV with a 50R load
Valid output with as little as 50mV input voltage difference
Propagation delay time - 1.7ns Typical driver and 3.7ns typical receiver
Power dissipation at 200MHz - 50mW Typical driver and 60mW typical receiver
LVTTL input levels are 5V tolerant
Driver is high-impedance when disabled or with VCC <1.5V
Green product and no Sb/Br

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