SN65LVDS048AD - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS048AD
Manufacturer

TI
ChipWorker Part#

CW31395763
Category

Interface IC, Interface Controller
Package

SOIC-16
Description

LVDS PHY (<800Mbps) Quad LVDS Receiver with Flow-Through Pinout LVDS Receiver 16Pin SOIC Tube
Documentation

Datasheet

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SN65LVDS048AD Specifications

Attribute	Attribute Value

Part Number	SN65LVDS048AD
Manufacturer	TI
ChipWorker Part#	CW31395763
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Supply Voltage (DC)	3.00V (min)
Supply Current	8 mA
Power Dissipation	774 W
Data Rate	400 Mbps
Output Current (Max)	100 mA
Input Current (Min)	20 µA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	950 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	9.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS048AD is a quad differential Line Receiver implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds and allow operation with a 3.3V supply rail. Any of the quad differential receivers will provide a valid logical output state with a ±100mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1V of ground potential difference between two LVDS nodes. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100R. The transmission media may be printed-circuit board traces, backplanes or cables.
Flow-through pin-out simplifies PCB layout
High impedance LVDS inputs on power-down
Low-power dissipation (40mW at 3.3V static)
Accepts small swing (350mV) differential signal levels
Supports open, short and terminated input failsafe
Conforms to TIA/EIA-644 LVDS standard
>400Mbps (200MHz) Signalling rate
50ps Typical channel-to-channel skew
200ps Typical differential skew
2.7ns Typical propagation delay time
3.3V Power supply design
Green product and no Sb/Br

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