SN65LVDS122PW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS122PW
Manufacturer

TI
ChipWorker Part#

CW27291483
Category

Logic Controller, Logic IC
Package

TSSOP-16
Description

Crosspoint-Switch (>1Gbps) 2X2 1.5Gbps LVDS Crosspoint Switch Digital Crosspoint Single 2x2 1.5Gbps 16Pin TSSOP Tube
Documentation

Datasheet

SN65LVDS122PW Global Supplier

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SN65LVDS122PW Specifications

Attribute	Attribute Value

Part Number	SN65LVDS122PW
Manufacturer	TI
ChipWorker Part#	CW27291483
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	3.00V (min)
Contacts Type	DPDT
Number of Positions	16 Position
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS122PW is a Crosspoint Switch that use low voltage differential signalling (LVDS) to achieve signalling rates as high as 1.5Gbps. They are pin-compatible speed upgrades to the SN65LVDS22. The internal signal paths maintain differential signalling for high speeds and low signal skews. This device has a 0 to 4V common-mode input range that accepts LVDS, LVPECL, CML inputs. Two logic pins (S0 and S1) set the internal configuration between the differential inputs and outputs. Additionally, SN65LVDT122 incorporates a 110- termination resistor for those applications where board space is a premium. Although this device is designed for 1.5Gbps, some applications at a 2Gbps data rate can be supported depending on loading and signal quality. The intended application of this device is ideal for loopback switching for diagnostic routines, fanout buffering of clock/data distribution provide protection in fault-tolerant systems.
Designed for signalling rates(1) up to 1.5Gbps
<65ps Total jitter
Inputs electrically compatible with CML, LVPECL and LVDS signal levels
Propagation delay of 900ps max

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