SN65LVDS179D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS179D
Manufacturer

TI
ChipWorker Part#

CW14973373
Category

Interface IC, Interface Controller
Package

SOIC-8
Description

LVDS PHY (<800Mbps) Single Full-Duplex LVDS Transceiver LVDS Driver/Receiver 0.454V 8Pin SOIC Tube
Documentation

Datasheet

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SN65LVDS179D Specifications

Attribute	Attribute Value

Part Number	SN65LVDS179D
Manufacturer	TI
ChipWorker Part#	CW14973373
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	3.00V (min)
Number of Positions	8 Position
Power Dissipation	635 W
Data Rate	400 Mbps
Input Current (Min)	20 µA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1110 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	4.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS179D is a high-speed differential Line Driver and Receiver uses low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400Mbps. The TIA/EIA-644 standard-compliant electrical interface provides a minimum differential output voltage magnitude of 247mV into a 100R load and receipt of 100mV signals with up to 1V of ground potential difference between a transmitter and receiver. This device offers various drivers, receiver and enabling combinations in industry-standard footprints. Because this device is intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state but rather disconnects the input and reduces the quiescent power used by the device.
Receiver has open-circuit failsafe design
Full-duplex signalling rate up to 150Mbps
Bus-pin ESD exceeds 12kV
LVTTL input levels are 5V tolerant
Low-voltage differential signaling with typical output voltage of 350mV and a 100R load
Propagation delay time - 1.7ns Typical driver and 3.7ns typical receiver
Power dissipation at 200MHz - 25mW Typical driver and 60mW typical receiver
Receiver maintains high input impedance with VCC<1.5V
Green product and no Sb/Br

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