SN65LVDS348PW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS348PW
Manufacturer

TI
ChipWorker Part#

CW27702400
Category

Interface IC, Interface Controller
Package

TSSOP-16
Description

LVDS PHY (<800Mbps) Quad LVDS Receiver with -4 to 5V Common-mode Range LVDS Receiver 560Mbps 16Pin TSSOP Tube
Documentation

Datasheet

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SN65LVDS348PW Specifications

Attribute	Attribute Value

Part Number	SN65LVDS348PW
Manufacturer	TI
ChipWorker Part#	CW27702400
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	3.00V (min)
Supply Current	20 mA
Number of Positions	16 Position
Power Dissipation	774 W
Data Rate	560 Mbps
Input Current (Min)	10 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	774 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS348PW is a quadruple high-speed Differential Receiver with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3V of ground noise or a variety of differential and single-ended logic levels. It offers flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. LVDT versions of both integrate a 110R line termination resistor. This receiver also provides 3x the standard minimum common-mode noise voltage tolerance. The -4 to 5V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS and LVCMOS levels without level shifting circuitry. Precise control of the differential input voltage thresholds allows for inclusion of 50mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50mV over the full input common-mode voltage range.
Flow-through architecture
Active failsafe assures a high-level output when an input signal is not present
Green product and no Sb/Br

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