SN65LVDS93ADGG - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS93ADGG
Manufacturer

TI
ChipWorker Part#

CW7048688
Category

Interface IC, Interface Controller
Package

TSSOP-56
Description

Flat Panel Display Link Serializer/Deserializer 135Mbps 1.8V/2.5V/3.3V 56Pin TSSOP Tube
Documentation

Datasheet

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SN65LVDS93ADGG Specifications

Attribute	Attribute Value

Part Number	SN65LVDS93ADGG
Manufacturer	TI
ChipWorker Part#	CW7048688
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	56 Pin
Case/Package	TSSOP-56
Number of Outputs	4 Output
Supply Current	102.2 mA
Number of Positions	56 Position
Data Rate	135 Mbps
Number of Inputs	28 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
	expand all
Size-Length	14.1 mm
Size-Width	6.2 mm
Size-Height	1.05 mm
Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS93ADGG is a LVDS SerDes (serializer/deserializer) FlatLink™ Transmitter contains four 7-bit parallel load serial-out shift registers, a 7 x clock synthesizer and five low-voltage differential signalling (LVDS) drivers in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94 (SLLS928). When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
LVDS display SerDes interfaces directly to LCD display panels with integrated LVDS
Suited for display resolutions ranging from HVGA up to HD with low EMI
Consumes less than 1mW when disabled
Selectable rising or falling clock edge triggered inputs
Supports spread spectrum clocking (SSC)
Compatible with all OMAP™2x, OMAP3x and DaVinci™ application processors
1.8 to 3.3V Tolerant data input to connect directly to low-power, low-voltage and graphic processors
10 to 135MHz Pixel clock frequency range
5kV HBM ESD
Green product and no Sb/Br

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