SN65LVDS93DGG - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS93DGG
Manufacturer

TI
ChipWorker Part#

CW28625676
Category

Interface IC, Interface Controller
Package

TSSOP-56
Description

Texas Instruments SN65LVDS93DGG, LVDS Serializer/Deserializer Quad 28Bits Driver, 3 → 3.6V, 56Pin, TSSOP
Documentation

Datasheet

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SN65LVDS93DGG Specifications

Attribute	Attribute Value

Part Number	SN65LVDS93DGG
Manufacturer	TI
ChipWorker Part#	CW28625676
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	56 Pin
Case/Package	TSSOP-56
Supply Voltage (DC)	3.00V (min)
Number of Outputs	4 Output
Number of Positions	56 Position
Power Dissipation	1377 W
Data Rate	1.90 Gbps
Number of Inputs	28 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1377 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	14 mm
Size-Width	6.1 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS93DGG is a Serdes (Serializer/Deserializer) Transmitter contains four 7-bit parallel- load serial-out shift registers, a 7x clock synthesizer and five low-voltage differential signalling (LVDS) drivers in a single integrated circuit. These functions allow 28-bit of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94. When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal. The rising or falling edge of the clock can be selected via the clock select pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN65LVDS93 requires no external components and little or no control.
Suited for point-to-point subsystem communication with very low EMI
Selectable rising or falling clock edge triggered inputs
No external components required for PLL
Replacement for the DS90CR285
28 Data channels/clock in low-voltage TTL and 4 data channels/clock out low-voltage differential
Bus pins tolerate 6kV HBM ESD
5V Tolerant data inputs
Consumes <1mW when disabled
Wide phase-lock input frequency range 20 to 68MHz
Green product and no Sb/Br

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