SN65LVDS95DGG - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS95DGG
Manufacturer

TI
ChipWorker Part#

CW9353646
Category

Interface IC, Interface Controller
Package

TSSOP-48
Description

Texas Instruments SN65LVDS95DGG, LVDS Serializer/Deserializer Triple 3Bits LVTTL 1428Mbit/s, 3 → 3.6V, 48Pin
Documentation

Datasheet

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SN65LVDS95DGG Specifications

Attribute	Attribute Value

Part Number	SN65LVDS95DGG
Manufacturer	TI
ChipWorker Part#	CW9353646
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	TSSOP-48
Supply Voltage (DC)	3.00V (min)
Number of Outputs	3 Output
Number of Channels	3 Channel
Number of Positions	48 Position
Power Dissipation	1316 mW
Data Rate	1.43 Gbps
Number of Inputs	21 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1316 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	12.5 mm
Size-Width	6.1 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

The SN65LVDS95DGG is a LVDS Serdes (Serializer/Deserializer) Transmitter contains three 7-bit parallel-load serial-out shift registers, a 7x clock synthesizer and four low-voltage differential signalling (LVDS) line drivers in a single integrated circuit. These functions allow 21-bit of single-ended LVTTL data to be synchronously transmitted over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96. When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising edge of the input clock signal. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The data bus appears the same at the input to the transmitter and output of the receiver with data transmission transparent to the user(s).
Suited for point-to-point subsystem communication with very low EMI
No external components required for PLL
Replacement for the National DS90CR215
21 Data channels/clock in low-voltage TTL and 3 data channels/clock out low-voltage differential
5V Tolerant data inputs
With rising clock edge triggered inputs
Bus pins tolerate 6kV HBM ESD
Consumes <1mW when disabled
3:21 Data channel compression at up to 1.428Gigabits/s throughput
Green product and no Sb/Br

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