SN65LVDS9637D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS9637D
Manufacturer

TI
ChipWorker Part#

CW38297700
Category

Interface IC, Interface Controller
Package

SOIC-8
Description

LVDS PHY (<800Mbps) Dual LVDS Receiver LVDS Receiver 150Mbps 8Pin SOIC Tube
Documentation

Datasheet

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SN65LVDS9637D Specifications

Attribute	Attribute Value

Part Number	SN65LVDS9637D
Manufacturer	TI
ChipWorker Part#	CW38297700
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	3.00V (min)
Supply Current	5.50 mA
Power Dissipation	725 mW
Data Rate	150 Mbps
Input Current (Min)	20 µA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	725 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	4.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS9637D is a Differential Line Receiver implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds and allow operation with a 3.3V supply rail. Any of the differential receivers provides a valid logical output state with a ±100mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1V of ground potential difference between two LVDS nodes. The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100R. The transmission media may be printed-circuit board traces, backplanes or cables.
Open-circuit failsafe
Low-voltage TTL (LVTTL) logic output levels
Cold sparing for space and high-reliability applications requiring redundancy
Pin-compatible with AM26LS32, MC3486 and µA9637
Operate from a single 3.3V supply
Bus-terminal ESD protection exceeds 8kV
150Mbps Signalling rate
±100mV Maximum differential input thresholds
2.1ns Typical propagation delay time
Power dissipation 60mW typical per receiver at maximum data rate
Green product and no Sb/Br

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