SN65MLVD040RGZT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65MLVD040RGZT
Manufacturer

TI
ChipWorker Part#

CW44500307
Category

LVDS, M-LVDS, ECL, CML IC
Package

VQFN-48
Description

Texas Instruments SN65MLVD040RGZT, LVDS Transceiver LVDS LVDS, 2CH, 3 → 3.6V, 48Pin, QFN
Documentation

Datasheet

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SN65MLVD040RGZT Specifications

Attribute	Attribute Value

Part Number	SN65MLVD040RGZT
Manufacturer	TI
ChipWorker Part#	CW44500307
Category	LVDS, M-LVDS, ECL, CML IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	VQFN-48
Supply Voltage (DC)	3.00V (min)
Number of Positions	48 Position
Power Dissipation	382 mW
Input Voltage (Max)	2 V
Input Voltage (Min)	0.8 V
Input Current (Min)	10 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	382 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	7.15 mm
Size-Width	7.15 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65MLVD040RGZT is a 4-channel half-duplex M-LVDS Line Transceiver for transmitting and receiving multipoint-low-voltage differential signals in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250Mbps. The driver output has been designed to support multipoint buses presenting loads as low as 30R and incorporates controlled transition times to allow for stubs off of the backplane transmission line. The M-LVDS standard defines two types of receivers, designated as type-1 and type-2. Type-1 receiver has thresholds centred about zero with 25mV of hysteresis to prevent output oscillations with loss of input, type-2 receiver implement a failsafe by using an offset threshold. The xFSEN pins is used to select the type-1 and type-2 receiver for each of the channels. In addition, the driver rise and fall times are between 1 and 2ns.
Controlled driver output voltage transition times for improved signal quality
Bus pins high impedance when driver disabled or VCC
Independent enables for each driver and receiver
M-LVDS bus power up/down glitch-free
125MHz Clock frequency
-1 to 3.4V Common-mode voltage range allows data transfer with 2V of ground noise
48 pin 7 X 7 QFN (RGZ)
Green product and no Sb/Br

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