SN65MLVD080DGG - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65MLVD080DGG
Manufacturer

TI
ChipWorker Part#

CW12363200
Category

Interface IC, Interface Controller
Package

TSSOP-64
Description

M-LVDS PHY (<500Mbps) 8Channel Half-Duplex M-LVDS transceiver LVDS Transceiver 64Pin TSSOP Tube
Documentation

Datasheet

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SN65MLVD080DGG Specifications

Attribute	Attribute Value

Part Number	SN65MLVD080DGG
Manufacturer	TI
ChipWorker Part#	CW12363200
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	64 Pin
Case/Package	TSSOP-64
Supply Voltage (DC)	3.00V (min)
Output Current	8 mA
Supply Current	180 mA
Number of Positions	64 Position
Input Current	180 mA
Power Dissipation	1839.4 W
Data Rate	250 Mbps
Input Current (Min)	10 μA
Number of Inputs	3 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1839.4 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	17 mm
Size-Width	6.1 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65MLVD080DGG is a 8-channel half-duplex M-LVDS Transceiver for transmitting and receiving Multipoint-Low-Voltage Differential Signals in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250Mbps. The driver outputs have been designed to support multipoint buses presenting loads as low as 30R and incorporates controlled transition times to allow for stubs off of the backbone transmission line. The receivers have thresholds centered about zero with 25mV of hysteresis to prevent output oscillations with loss of input. In addition, the driver rise and fall times are between 1 and 1.5ns, complying with the M-LVDS standard to provide operation at 250Mbps while also accommodating stubs on the bus. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.
Low-voltage differential 30R line drivers and receivers
Meets or exceeds the M-LVDS standard TIA/EIA-899 for multipoint data interchange
Controlled driver output voltage transition times for improved signal quality
1 to 3.4V Common-mode voltage range allows data transfer
Bus pins high impedance when driver disabled or VCC
Independent enables for each driver
Bus pin ESD protection exceeds 8kV

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